During the keynote speech at Intel’s Innovation event in San Jose, CEO Pat Gelsinger revealed around 20 details about the upcoming Meteor Lake client platform. Intel’s Meteor Lake marks the start of a new era for the chipmaker, as it moves away from the chaotic Intel 7 node and begins rolling out its Foveros 3D packaging with EUV lithography for its next mobile platform customer. Meteor Lake uses a tiled, disaggregated chip architecture for its customer-centric processors for the first time, changing the very nature of Intel’s consumer chips going forward. And, according to Intel, all these changes have allowed them to bring significant advances to the mobile market.
The first mainstream processor based on Intel chipsets divides the common functions of a modern processor into four individual tiles: compute, graphics, SoC, and an I/O tile. The compute tile includes a new pair of cores, a P core named Redwood Cove and a new E core called Crestmont. Both of these cores promise IPC gains over their previous counterparts, but perhaps the most interesting inclusion is a new E-core type integrated directly into the SoC tile, which Intel calls “Low Power Island.” These new LP E cores are designed with the idea that lightweight workloads and processes can be removed from the most power-hungry compute tile and offloaded to a more efficient, less power-hungry tile. Other major additions include an Intel-first Neural Processing Unit (NPU), which sits in the SoC tile and is designed to bring on-chip AI capabilities for workloads and inference, opening up the way to the future.
With Meteor Lake, Intel aims to put itself in a more competitive position in the mobile market, with notable improvements to the compute core hierarchy, as Intel’s Xe-LPG Arc-based graphics tile seeks to boost integrated graphics capabilities and an NPU that adds various AI Benefits. Meteor Lake also paves the way for Intel and modular disaggregation, with Foveros 3D packaging set to become a pillar of Intel’s processor roadmap for the future, with the Intel 4 process debuting and acting as a stepping stone towards which will become the next pillar of Intel. node in its factories, Intel 3.
Intel Meteor Lake: Intel 4 using Foveros 3D packaging
Intel’s Meteor Lake architecture isn’t just another iteration in a long line of processor advancements; according to the company, this is a revolutionary step forward. Eloquently delivered by Executive Vice President and General Manager of Intel’s Client Computing Group (CCG), Michelle Johnston Holhaus, at Intel’s Tech Tour 2023 in Penang, Malaysia, she noted that Intel has achieved an inflection point in its customer roadmap. Unveiling more details about Meteor Lake at the Intel Technology Tour in Malaysia, the architecture is a step up from its current client processors in terms of performance as we progress through Intel’s ‘5-node’ roadmap in 4 years.
Meteor Lake is built on Intel’s disaggregated architecture driven by Foveros packaging. This is designed to optimize both performance and energy efficiency. The architecture itself consists of four unique and distinct tiles connected via Intel’s Foveros 3D packaging technology. This includes the compute tile, which is built on Intel 4, while the graphics tile is built on TSMC’s N5 node. The other two tiles that Intel implements in Meteor Lake are the SoC tile which acts as a central hub via the integrated NOC. This is the first time Intel has used network-on-chip (NOC) on its client processors, providing a simplified approach to NOC on its existing Agilex FPGAs. While on Agilex the NOC is individualized into different NoC targets and switches within the NoC substructure, on Meteor Lake it connects directly to the I/O fabric via the IoC, which then goes into the I/O structure. The NOC itself is directly connected to the graphics tile, compute tile, and other components of the SoC.
This modular approach enables a basic, scalable energy management architecture that supports disaggregation, allowing each tile to operate independently. This disaggregated design prioritizes performance by eliminating bandwidth bottlenecks through elements such as I/O over a monolithic design and aims for improved power efficiency. Perhaps the most notable disaggregation element is that Intel can select specific silicon processes for each tile and is not limited to a single process node. In addition to the power efficiency and benefits of a tiled architecture, it is cheaper for Intel to make processors with fewer masks via EUV, but it allows Intel to extend the new IP to future products while still keeping the same base, which is another advantage. saving factor (for Intel).
Compared to the mobile Raptor Lake, which was made using multi-chip packaging (MCP), Meteor Lake uses Foveros BGA packaging and features low-power die-to-die interconnects, which Intel says , has a slight power penalty of between 0.15 and 0.3 picojoules. (pJ) communicating from tile to tile. Some of the benefits of Foveros include better customization through tiling, which allows Intel to manufacture chips and implement specific tiles and IP based on chip quality, etc., low power with more I/O, or high-end tiles with all the latest bells and whistles. With the Intel 7 node not being as viable as they would have hoped, Intel is promising higher wafer efficiency on Intel 4, which uses less wafer space for logic silicon.
Energy management is accomplished using a scalable energy management system that supports independent operation of each tile. Coordination between multiple power management controllers (PMCs) and system software is designed to be optimized for various workloads. Intel’s Meteor Lake architecture also introduces a new scalable framework to improve power efficiency and expand bandwidth in previously bottlenecked areas, such as I/O.
Further addressing power controllers within the Meteor Lake architecture, Intel has integrated independent power management controllers into each of the tiles. As part of the disaggregation of using Foveros, each tile must be managed independently of power, and the use of PMC on the NOC, I/O fabric, as well as each tile allows management of power to be agnostic based on the number of cores on each package.
Meteor Lake itself represents a monumental architectural change, and not just a simple incremental update, as it represents the most significant architectural transformation of client processors in four decades. Indeed, it is the first client processor to be manufactured using chipsets instead of a monolithic design. The architecture is designed to be the cornerstone of Intel’s strategy to drive PC innovation over the next decade. Looking at some of the finer details of Intel’s Meteor Lake architecture, it uses Intel’s Foveros packaging technology, which uses 3D chip stacking to overcome the pitfalls of traditional 2D chip layouts.
As we can see in Intel’s Hot Chips 2023 disclosure above, both the top and bottom layers feature bumps to interconnect each chip. Using the Foveros FDI package offers a low voltage Complementary Metal Oxide Semiconductor (CMOS) interface, meaning power circuits can operate with lower voltages and, therefore, a lower power envelope. Another advantage of FDI is both synchronous and asynchronous signaling, which means the signal transmission can handle fully duplexed blocks of data.
The construction of a Meteor Lake SoC includes a package substrate, which forms the foundation upon which the base plate rests, which uses the Foveros Die Interconnect (FDI). The base panel has a chip-to-chip pitch of 36 µm with a metal layer and an operating power of 0.15 to 0.3 pJ at 2 GHz; this can fluctuate or vary depending on voltages, amps and frequency. As it is a basic tile which is not an active chiplet itselfits only function is to serve as the basis for all the different logics, and as metal layers for the chiplets be placed on it.
Intel’s Meteor Lake architecture composition uses four distinct tiles to create a Meteor Lake processor. This includes compute, SoC, GPU, and I/O tile, all with distinct IP uses, capabilities, and flexibility. Power management is also getting an overhaul. Thanks to disaggregation using Intel’s Foveros packaging technology, each tile in Meteor Lake requires its own power management. Intel’s solution is a hierarchical power management system that uses power management controllers on the NoC, IO fabric, and each individual tile.
Over the next few pages, we’ll provide an overview of each of the four tiles, what each tile brings, and more about the different technologies that are driving innovation through Meteor Lake.
